Semiconductor devices having a convex active region

ABSTRACT

Methods of forming a semiconductor device include forming a trench mask pattern on a semiconductor substrate having active regions and device isolation regions. A thermal oxidation process is performed using the trench mask pattern as a diffusion mask to form a thermal oxide layer defining a convex upper surface of the active regions. The thermal oxide layer and the semiconductor substrate are etched using the trench mask pattern as an etch mask to form trenches defining convex upper surfaces of the active regions. The trench mask pattern is removed to expose the convex upper surfaces of the active regions. Gate patterns are formed extending over the active regions.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No.11/642,198 filed Dec. 20, 2006 which is related to and claims priorityunder 35 USC § 119 from Korean Patent Application No. 2006-83652, filedon Aug. 31, 2006 in the Korean Intellectual Property Office, thedisclosures of which are incorporated herein by reference in theirentireties.

BACKGROUND OF THE INVENTION

The present invention disclosed herein relates to semiconductor devicesand methods of forming the same, and more particularly, to semiconductordevices having a convex active region and methods of forming the same.

Generally, a field effect transistor (FET) includes an active region, agate electrode crossing over the active region and source/drainelectrodes formed adjacent to the gate electrode. The active regionunder the gate electrode is used as a channel region that provides amoving path for charges between source/drain regions formed in theactive region on respective sides of the gate electrode. In other words,the channel region is the active region between the source and drainelectrodes.

As the integration density of semiconductor devices increases, thewidths of the gate electrodes and active regions have generally beenreduced. However, as the width of the gate electrode is reduced, alength of the channel region (i.e., a space between the source regionand the drain region) is also reduced. If the width of the active regionis reduced, the width of the channel region may also be reduced, whichmay cause a narrow width effect that generally decreases a draincurrent.

In recent years, to address technical problems, including the shortchannel effect or the narrow channel effect, a fin-FET having afin-shaped active region has been proposed. In the fin-FET, as a facingarea between the gate electrode and the channel region is increased, thechannel width can be increased, in comparison with a planar FET, and anelectric potential of the channel region can be effectively controlled.

However, in a typical conventional fin-FET, a conductive residue may beformed between gate electrodes, which may result in a gate bridgephenomenon. More specifically, FIGS. 1A and 1B are perspective viewsillustrating the gate bridge occurring in a conventional method offabricating a fin-FET.

Referring to FIGS. 1A and 1B, a device isolation pattern 20 is formed ona predetermined region of a semiconductor (integrated circuit) substrate10 to define active regions 15. The device isolation pattern 20 isrecessed to expose a top surface and upper portions of sidewalls(hereinafter, referred to as upper sidewalls) of the active regions 15.A gate insulating layer 25 is formed on the top surface and the uppersidewalls of the exposed active regions 15. A gate conductive layer 30is formed on the semiconductor device in the region where the gateinsulating layer 25 is formed.

As seen in FIG. 1B, the gate conductive layer 30 is patterned to formgate patterns 35 crossing over the active regions 15. The forming of thegate patterns 35 includes etching the gate conductive layer 30 until thetop surfaces of the device isolation pattern 20 and the active regions15 are exposed.

Due to a height difference between the active regions 15 and the deviceisolation pattern 20, a deposition thickness h₁ of the gate conductivelayer 30 is smaller than a vertical thickness h₂ of the gate conductivelayer 30 at the side of the active regions 15. Due to this thicknessdifference, a conductive residue 50 electrically connecting the gatepatterns 35 to each other may be formed on the side surfaces of theactive regions 15 as a result of the etching process used in patterningthe gate conductive layer 30. The conductive residue 50 may causedefects, such as the gate bridge.

A conventional floating gate type flash memory device may have varioustechnical problems caused by increasing an aspect ratio of a gatepattern in high-density devices. To address such problems, a charge trap(floating gate) type nonvolatile memory device has been proposed, whichincludes a tunneling insulating layer (interposed between the activeregion and the gate electrode), a charge storage layer, and a blockingdielectric layer. However, due to the increase of the aspect ratio of agap region with the high integration devices, it is generally necessaryto reduce the thickness of the blocking dielectric layer. If thethickness of the blocking dielectric layer is not reduced, the facingarea between the gate pattern and the charge storage layer may bereduced by the blocking dielectric layer filling an upper portion of thegap region. However, reducing the thickness of the blocking dielectriclayer may cause problems with an electrical property of the memory cell,which may be deteriorated due to leakage current.

SUMMARY OF THE INVENTION

Some embodiments of the present invention provide methods of forming asemiconductor device. A trench mask pattern is formed on a semiconductorsubstrate having active regions and device isolation regions. A thermaloxidation process is performed using the trench mask pattern as adiffusion mask to form a thermal oxide layer defining a convex uppersurface of the active regions. The thermal oxide layer and thesemiconductor substrate are etched using the trench mask pattern as anetch mask to form trenches defining convex upper surfaces of the activeregions. The trench mask pattern is removed to expose the convex uppersurfaces of the active regions. Gate patterns are formed extending overthe active regions.

In further embodiments, etching the thermal oxide layer is followed byforming device isolation patterns filling the trenches. Forming thetrench mask pattern includes forming an oxide pattern on thesemiconductor substrate and forming a nitride pattern as the diffusionmask on the oxide pattern. Forming the trench mask pattern may includeforming the oxide layer and the nitride layer on the semiconductorsubstrate and patterning the oxide layer and the nitride layer to formthe trench mask pattern defining preliminary cell trenches. Thepreliminary cell trenches are formed on the device isolation regions andbottom surfaces of the preliminary cell trenches are lower than a topsurface of the semiconductor substrate in the active regions. A radiusof curvature of the convex upper surface of the active regions and athickness of the thermal oxide layer at edges of the trench mask patternmay be controlled based on a height difference between the bottomsurface of the preliminary cell trench and the top surface of thesemiconductor substrate in the active regions.

In other embodiments, performing the thermal oxidation process includesperforming the thermal oxidation process in a temperature range of about600 to about 1,500 degrees Celsius for about 10 seconds to about 1 hourin a gas ambient including oxygen atoms. Performing the thermaloxidation process may include performing the thermal oxidation processto provide a thickness of the thermal oxide layer under edge portions ofthe trench mask pattern greater than a thickness of the thermal oxidelayer under a central portion of the trench mask pattern. Forming thenitride pattern may include forming the nitride pattern to a thicknessthat limits oxygen diffusion while performing the thermal oxidationprocess to provide the thickness of the thermal oxide layer under theedge portions greater than the thickness of the thermal oxide layerunder the central portion.

In further embodiments, forming the gate patterns includes recessing thedevice isolation regions to expose sidewalls of the active regions andforming a cell gate layer on the active regions and the recessed deviceisolation pattern. The cell gate layer includes a tunnel insulatinglayer, a charge storage layer, a blocking dielectric layer and a cellgate electrode layer. The cell gate layer is patterned to form the gatepatterns extending over the active regions. The cell gate electrodelayer may be a metal nitride and the charge storage layer may be anoxide and/or nitride of silicon, metal and/or metal silicide and theblocking insulating layer may be an insulating material having a higherdielectric constant than a dielectric constant of the charge storagelayer. The charge storage layer may be a silicon nitride layer, theblocking dielectric layer may be an aluminum oxide layer and the cellgate electrode layer may be a tantalum nitride layer. Forming the cellgate layer may be preceded by forming hemispherical silicon grains onthe convex upper surface of the active regions.

In other embodiments, the semiconductor substrate includes a cell arrayregion and a peripheral circuit region. Etching the thermal oxide layerincludes forming a photoresist layer covering the cell array region andexposing the peripheral circuit region, etching the semiconductorsubstrate using the photoresist pattern and the trench mask pattern asan etch mask to form preliminary peripheral trenches in the peripheralcircuit region, removing the photoresist pattern and then etching thesemiconductor substrate of the cell array region and the bottom surfacesof the preliminary peripheral trenches of the peripheral circuit regionusing the trench mask pattern as an etch mask to form cell trenches inthe cell array region and peripheral trenches in the peripheral circuitregion. A depth of the peripheral trench may be substantially equal to asum of a depth of the preliminary peripheral trench and a depth of thecell trench.

In yet further embodiments, forming the gate patterns includes formingcell gate patterns in the cell array region and forming peripheral gatepatterns in the peripheral circuit region. Forming the cell gatepatterns includes forming a tunnel insulating pattern on thesemiconductor substrate, forming a charge storage pattern on the tunnelinsulating pattern, forming a blocking dielectric pattern on the chargestorage pattern and forming a cell gate electrode on the blockingdielectric pattern. Forming the peripheral gate patterns includesforming a peripheral gate insulating pattern on the semiconductorsubstrate and forming a peripheral gate conductive pattern on theperipheral gate insulating pattern.

In other embodiments, forming the cell gate patterns includes recessingthe device isolation regions in the cell array region to exposesidewalls of the active regions in the cell array region. A cell gatelayer, including a tunnel insulating layer, a charge storage layer, ablocking dielectric layer and a cell gate electrode layer, is formed onthe recessed device isolation regions and the active regions in the cellarray region. The cell gate layer is patterned to form the cell gatepatterns extending over the active regions.

In further embodiments, forming the gate patterns includes forming aperipheral gate layer on the semiconductor structure in a region wherethe trench mask patterns are removed. The peripheral gate layer ispatterned to remove the peripheral gate layer from the cell arrayregion. The device isolation regions are recessed in the cell arrayregion to expose sidewalls of the active region in the cell arrayregion. A cell gate layer is formed on the recessed device regions andactive areas in the cell array region. The cell gate layer is patternedto form the gate patterns extending over the active regions.

In further embodiments, forming the cell gate layer includes forming atunnel insulating layer on the semiconductor substrate, forming a chargestorage layer on the tunnel insulating layer, forming a blockingdielectric layer on the charge storing layer and forming a cell gateelectrode layer on the blocking dielectric layer. Forming the peripheralgate layer includes forming a peripheral gate insulating layer on thesemiconductor substrate and forming a peripheral gate conductive layeron the peripheral gate insulating layer. Forming the gate patternsincludes removing the cell gate layer from the peripheral circuitregion.

In yet other embodiments, semiconductor devices includes a semiconductorsubstrate comprising a cell array region and cell device isolationpatterns in the cell array region that define cell active regions havinga convex upper surface. Cell gate patterns cross over the convex uppersurfaces of the cell active regions and over the cell device isolationpatterns. The semiconductor substrate may further include a peripheralcircuit region. The convex upper surfaces may have a radius of curvaturethat is about 1/10 to about ½ of a width thereof and a top surface ofthe cell device isolation pattern may be lower than the convex uppersurfaces.

In further embodiments, the device further includes peripheral deviceisolation patterns in the peripheral circuit region that defineperipheral active regions. A peripheral gate pattern is on theperipheral active regions. The peripheral gate patterns includes astacked peripheral gate insulating layer and a peripheral gateconductive layer. The cell gate patterns includes a stacked tunnelinsulating layer, charge storage layer, blocking dielectric layer andcell gate electrode layer. The peripheral gate conductive layer may be apolysilicon layer, the cell gate electrode layer may be a metal nitride,the charge storage layer may be an oxide and/or nitride of silicon,metal and/or metal silicide, and the blocking insulating layer may be aninsulating material having a higher dielectric constant than adielectric constant of the charge storage layer. The charge storagelayer may be a silicon nitride layer, the blocking dielectric layer maybe an aluminum oxide layer, and the cell gate electrode layer may be atantalum nitride layer.

In some embodiments, a height of a top surface of the peripheral deviceisolation pattern is no less than a height of a top surface of theperipheral active region. A first portion of the peripheral gate patternmay be a low voltage transistor, and a second portion of the peripheralgate pattern may be a high voltage transistor. The peripheral gateinsulating layer of the peripheral gate pattern may providing the highvoltage transistor may be thicker than the peripheral gate insulatinglayer of the peripheral gate pattern providing the low voltagetransistor. The device may further include hemispherical silicon grainsbetween the cell active regions and the cell gate patterns, thehemispherical silicon grains extending from the semiconductor substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a furtherunderstanding of the invention and are incorporated in and constitute apart of this application, illustrate some embodiments of the inventionand together with the description serve to explain the invention. In thedrawings:

FIGS. 1A and 1B are perspective views illustrating a gate bridgeresulting from a method of fabricating a fin-FET according to the priorart;

FIG. 2 is a plan view illustrating a portion of a cell array of asemiconductor device according to some embodiments of the presentinvention;

FIGS. 3A through 13A and FIGS. 3B through 13B are cross-sectional viewsillustrating a method of forming a semiconductor device according tosome embodiments of the present invention; and

FIG. 14 is a cross-sectional view of a semiconductor device according tosome embodiments of the present invention.

DETAILED DESCRIPTION

The invention is described more fully hereinafter with reference to theaccompanying drawings, in which embodiments of the invention are shown.This invention may, however, be embodied in many different forms andshould not be construed as limited to the embodiments set forth herein.Rather, these embodiments are provided so that this disclosure will bethorough and complete, and will fully convey the scope of the inventionto those skilled in the art. In the drawings, the size and relativesizes of layers and regions may be exaggerated for clarity.

It will be understood that when an element or layer is referred to asbeing “on”, “connected to” or “coupled to” another element or layer, itcan be directly on, connected or coupled to the other element or layeror intervening elements or layers may be present. In contrast, when anelement is referred to as being “directly on,” “directly connected to”or “directly coupled to” another element or layer, there are nointervening elements or layers present. Like numbers refer to likeelements throughout. As used herein, the term “and/or” includes any andall combinations of one or more of the associated listed items.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, components, regions, layersand/or sections, these elements, components, regions, layers and/orsections should not be limited by these terms. These terms are only usedto distinguish one element, component, region, layer or section fromanother region, layer or section. Thus, a first element, component,region, layer or section discussed below could be termed a secondelement, component, region, layer or section without departing from theteachings of the present invention.

Spatially relative terms, such as “beneath”, “below”, “lower”, “above”,“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the exemplary term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

Embodiments of the present invention are described herein with referenceto cross-sectional illustrations that are schematic illustrations ofidealized embodiments of the present invention. As such, variations fromthe shapes of the illustrations as a result, for example, ofmanufacturing techniques and/or tolerances, are to be expected. Thus,embodiments of the present invention should not be construed as limitedto the particular shapes of regions illustrated herein but are toinclude deviations in shapes that result, for example, frommanufacturing. For example, an etched region illustrated as a rectanglewill, typically, have rounded or curved features. Thus, the regionsillustrated in the figures are schematic in nature and their shapes arenot intended to illustrate the precise shape of a region of a device andare not intended to limit the scope of the present invention.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andthis specification and will not be interpreted in an idealized or overlyformal sense unless expressly so defined herein.

FIG. 2 is a plan view illustrating a portion of a cell array of asemiconductor device according to some embodiments of the presentinvention. FIGS. 3A through 13A and FIGS. 3B through 13B arecross-sectional views illustrating a method of forming a semiconductordevice according to some embodiments of the present invention. Morespecifically, FIG. 2 illustrates a portion of a cell array of a NANDflash memory. FIGS. 3A through 13A are cross-sectional views taken alonga dotted line I-I′ of FIG. 2 and FIGS. 3B through 13B arecross-sectional views illustrating a portion of a peripheral circuitregion of the semiconductor device of FIGS. 3A through 13A,respectively.

Referring first to FIGS. 2 and 13A, the semiconductor device 100includes a cell array region CAR and a peripheral circuit region. In thecell array region CAR, recessed device isolation patterns 165 aredisposed defining cell active regions. The top surface of the recesseddevice isolation pattern 165 is lower than the top surface of the cellactive region, such that the cell active region has the shape of a fin.A ground select line GSL, a string select line SSL and a plurality ofcell gate patterns 260, which cross over the cell active regions, areprovided extending over the recessed device isolation pattern 165. Thecell gate patterns 260 are shown disposed between the ground and stringselect lines GSL and SSL. At one side of the ground select line GSL, acommon source line CSL is shown disposed in parallel with the cell gatepatterns 260. Bit line plugs 199 are shown disposed at one side of thestring select line SSL. The bit line plugs 199 are connected to a bitline (not shown) crossing over the cell gate patterns 260.

In some embodiments of the present invention, the cell active region hasa convex upper surface with a predetermined radius of curvature (see,e.g., FIG. 13A). In some embodiments of the present invention, the uppersurface of the cell active region does not have a flat portion thereofwhile in other embodiments the convex upper surface may include a flatportion thereof (see, e.g., FIG. 7A). The term top surface and uppersurface may be used interchangeably herein with reference to the cellactive region and, in either case, a portion of the upper/top surfacemany not be fully rounded or convex in some embodiments. It will furtherbe understood that references to the active region with a gate patternextending thereon refers to a channel region of a cell device formed inthe active region.

In addition, the top surface of the cell active region in someembodiments has a radius of curvature that is about 1/10 to ½ of thewidth thereof. Accordingly, a contour line from a central portion of thecell active region to edges thereof may be gently sloping. As a resultof such a gentle slope of the top surface of the cell active region, thethickness of the cell gate pattern 260 may not vary much between thecentral portion of the cell active region and the edges thereof, whichmay be significantly different from the prior art device structure. As aresult, it may be possible to reduce problems with the prior art, suchas a conductive residue.

As seen in FIG. 13A, in some embodiments of the present invention, thecell gate pattern 260 includes a tunnel insulating pattern 205, a chargestorage pattern 215, a blocking dielectric pattern 225, a cell gateelectrode 235 and an upper gate electrode 255, which are sequentiallystacked. In some embodiments, the tunnel insulating layer 205 may be asilicon oxide layer having a thickness ranging from about 10 Å to about200 Å formed by thermal oxidation process. The charge storage pattern215 in some embodiments may be an oxide and/or nitride of silicon, metaland/or metal silicide. For example, the charge storage pattern 215 maybe a silicon nitride layer formed to a thickness ranging from about 20 Åto about 200 Å. In addition, the blocking dielectric pattern 225 may beformed of insulating materials having a higher dielectric constant thanthe charge storage pattern 215 or the tunnel insulating pattern 205. Insome embodiments the charge storage pattern 215 is a silicon nitridelayer and the blocking dielectric pattern 225 may be a high dielectriclayer or layers, such as an aluminum oxide layer (Al₂O₃), a hafniumoxide layer (HfO₂) and/or the like, and the blocking dielectric pattern225 may have a thickness ranging from about 50 Å to about 300 Å.

When the blocking dielectric pattern 225 has high dielectric constant, aback-tunneling between the charge storage pattern 215 and the cell gateelectrode 235 may be reduced and a coupling ratio may be increased sothat it may be possible to fabricate a floating trap type nonvolatilememory device more stably and effectively. The cell gate electrode 235may be formed of one or more metal nitrides. In some embodiments, thecell gate electrode 235 may be a tantalum nitride layer (TaN) having athickness ranging from about 100 Å to about 1,000 Å

Referring now to FIGS. 3A and 3B, after a trench mask layer is formed ona semiconductor substrate 100 having a cell array region CAR and aperipheral circuit region, the trench mask layer is patterned to form atrench mask pattern 110 defining active regions and device isolationregions. Specifically, the trench mask pattern 110 is disposed on theactive region to expose the semiconductor substrate 100 of the deviceisolation region. Here, the peripheral circuit region will be describedfor illustrative purposes as including a low voltage region LVR wherelow-voltage transistors are disposed, and a high voltage region HVR,where high-voltage transistors are disposed.

In some embodiments, the trench mask pattern 110 may be a sequentiallystacked oxide pattern 111 and nitride pattern 112. The oxide pattern 111may be a silicon oxide layer formed by a thermal oxidation processand/or a chemical vapor deposition (CVD) process. The oxide pattern 111may have a thickness ranging from about 10 A to about 250 A The nitridepattern 112 may be a silicon nitride layer formed by CVD process, andmay have a thickness ranging from about 50 Å to about 1,000 Å The trenchmask pattern 110 may further include a capping pattern (not shown)disposed on the nitride pattern 112. The capping pattern may be asilicon oxide layer, such as a medium temperature oxide (MTO) or thelike.

In some embodiments, patterning the trench mask layer may includerecessing a top surface of the semiconductor substrate 100 to apredetermined depth d1. In this case, as shown in FIG. 3A, preliminarycell trenches 121 having bottom surfaces lower than the top surface ofthe semiconductor substrate 100 are formed between the trench maskpatterns 110 to expose sidewalls of the oxide pattern 111.

The peripheral circuit region may be entirely covered with the trenchmask pattern 110 as shown in FIG. 3B. However, in some embodiments ofthe present invention, portions of the substrate 100 may be exposed bythe trench mask patterns 110 in the peripheral circuit region as well asthe cell array region CAR.

Referring now to FIGS. 4A and 4B, a thermal oxidation process isperformed using the trench mask pattern 110 as a mask to form a thermaloxide layer 130 on a bottom surface of the preliminary cell trench 121.The thermal oxidation process may be performed in a temperature range ofabout 600-1,500 degrees Celsius (C) for about 10 seconds to about 1 hourin a gas ambient containing oxygen atoms. The thermal oxidation processmay be performed in a temperature range of about 900-1,100 degreesCelsius for about 5-15 minutes in an oxygen and/or ozone gas ambient.The oxygen atoms may diffuse under the nitride pattern 112 to react withsilicon atoms of the semiconductor substrate 100, thereby increasing thethickness of the oxide pattern 111. Thus, it can be understood that thethermal oxide layer 130 may be a silicon oxide layer formed by thethermal oxidation process and including portions of the oxide pattern111 of the trench mask pattern 110.

Because the oxygen atoms generally barely penetrate the nitride pattern112, the nitride pattern 112 may be used as a diffusion mask that limitsor even prevents the penetration of the oxygen atoms. Thus, as thelength (distance) from the sidewalls of the trench mask pattern 110increases, the penetration probability of the oxygen atoms may bedecreased. The variation of the length-dependent penetration probabilityof the oxygen atoms may cause the thickness of the thermal oxide layer130 to vary based on the length (distance) from the sidewalls of thetrench mask pattern 110. That is, the thickness of the thermal oxidelayer 130 in some embodiments is greater at edges of the trench maskpattern 110 than in a central portion thereof. A shape change of thesilicon oxide layer according to the above mechanism is generally calleda bird's beak phenomenon.

As the bird's beak phenomenon typically causes the channel length of thetransistor or the channel width to be reduced, various conventionaltechnologies have been proposed for minimizing the bird's beakphenomenon. In contrast, for some embodiments of the present invention,there may be no technical problem caused by the bird's beak because thesilicon oxide layer additionally formed through the thermal oxide layeris not used as the gate insulating layer of the transistor. Furthermore,as the integration degree of the semiconductor device increases, thewidth of the silicon oxide layer, of which the thickness increases dueto the bird's beak, may become as great as the width of the trench maskpattern 110. Thus, the bird's beak phenomenon can be used in someembodiments for adjusting the radius curvature of the top surface of thesemiconductor substrate disposed under the trench mask pattern 110.

The processing conditions of the thermal oxidation process, e.g., time,temperature and/or oxidation gas, may be process parameters affectingthe bird's beak phenomenon. Therefore, it is possible to adjust theradius of curvature of the top surface of the semiconductor substrate100 under the trench mask pattern 110, i.e., the top surface of theactive region under the trench mask pattern 110, by controlling theseprocess parameters. In addition, a height difference (see dl of FIG. 3A)between the bottom surface of the preliminary cell trench 121 and thetop surface of the semiconductor substrate 100 of the active regiongenerally has an effect on a diffusion rate of the oxygen atom in thethermal oxidation process and the thickness of the thermal oxide layer130 at edges of the trench mask pattern 110. Thus, a method ofcontrolling the depth of the preliminary cell trench 121 may be used asa method of adjusting the radius of curvature of the top surface of theactive region.

As described above, the trench mask pattern 110 may completely cover theperipheral circuit region. In this case, because the nitride pattern 112acts as a diffusion mask, the thickness of the oxide pattern 111 in theperipheral circuit region may be unchanged (uniform).

Referring next to FIGS. 5A and 5B, the trench mask pattern 110 ispatterned in the peripheral circuit region to define the peripheralcircuit region. Preliminary peripheral trenches 151 are formed in theperipheral circuit region using the patterned trench mask pattern 110 asan etch mask. Forming the preliminary peripheral trenches 151 mayinclude forming a first photoresist pattern 140 covering the cell arrayregion CAR but exposing the peripheral circuit region and etching thesemiconductor substrate 100 of the peripheral circuit region using thefirst photoresist pattern 140 and the trench mask pattern 100 as an etchmask.

In some embodiments, the first photoresist pattern 140 may be used as anetch mask for patterning the trench mask pattern 110. In this case, thefirst photoresist pattern 140 is formed on the trench mask pattern 110of the peripheral circuit region to define the trench mask pattern 110.

Referring now to FIGS. 6A and 6B, the first photoresist pattern 140 isremoved to expose the cell array region CAR. The exposed semiconductorsubstrate 100 is anisotropically etched using the trench mask pattern110 as an etch mask. Accordingly, a cell trench 155 is formed in thecell array region CAR to define the cell active region and a peripheraltrench 152 is formed in the peripheral circuit region to define theperipheral active region.

The peripheral trench 152 is formed by further etching the preliminaryperipheral trench 151 during the etching process for forming the celltrench 155. Thus, the peripheral trench 152 may be deeper than the celltrench 155. More specifically, the depth D1′ of the peripheral trench152 is shown as being substantially equal to a summation of the depth D2of the cell trench 155 and the depth D1 of the preliminary peripheraltrench 151.

Referring to FIGS. 7A and 7B, a device isolation pattern 160 is shownformed to fill the cell and peripheral trenches 155 and 152. Forming thedevice isolation pattern 160 may include forming a device isolationlayer on the structure where the cell and peripheral trenches 155 and152 are formed and performing a planarization process to etch the deviceisolation layer until the top surface of the trench mask pattern 110 isexposed. The planarization process may be performed using a chemicalmechanical polishing (CMP) process.

The device isolation layer may be a silicon oxide layer, a siliconnitride layer, a polysilicon layer, an epitaxial silicon layer and/or alow dielectric layer. In some embodiments, the device isolation layer isformed of silicon oxide.

In some embodiments, before forming the device isolation layer, a trenchthermal oxidation process may performed to form trench oxide layers oninner walls of the cell and peripheral trenches 155 and 152. The trenchthermal oxidation process may have an effect on the structure of thethermal oxide layer 130 under the trench mask pattern 110 and the radiusof curvature of the top surface of the cell active region. Therefore, inorder to make the top surface of the cell active region have a radius ofcurvature with a desired dimension, a method of controlling processconditions of the trench thermal oxidation process may be utilized.

In addition, according to some embodiments, a nitride liner may beformed on the inner walls of the cell and peripheral trenches 155 and152. When forming the trench oxide layer in some embodiments, thenitride liner can be formed between the trench oxide layer and thedevice isolation pattern. The nitride liner may play a role in limitingor even preventing impurities from diffusing into the active regions,which may stabilize the characteristic of the transistor.

Referring to FIGS. 8A and 8B, the trench mask pattern 110 is removed toexpose the top surface of the cell active region and the top surface ofthe peripheral active region. Removing the trench mask pattern 110 mayinclude removing the nitride pattern 112 to expose the oxide pattern 111and removing the exposed oxide pattern 111 using an etch recipe havingan etch selectivity with respect to the semiconductor substrate 100. Asused herein, references to the etching of B material using an etchrecipe having an etch selectivity with respect to A material means thatthe etch process is performed using the etch recipe enabling the Amaterial to be etched minimally but the B material to be etchednormally. Removing the nitride pattern 112 may be performed using anetch solution containing phosphoric acid, and removing the oxide pattern11 may be performed using an etch solution containing hydrofluoric acid.

The device isolation pattern 160 may be formed of a silicon oxide layeras described above. In this case, removing the oxide pattern 111 withthe etch solution containing hydrofluoric acid may be performed byetching an exposed upper region of the device isolation pattern 160.

In some embodiments, after removing the trench mask pattern 110, an ionimplantation process may be additionally performed onto the exposed cellactive region and peripheral active region to adjust impurityconcentrations of channel regions of transistors.

Referring to FIGS. 9A and 9B, a peripheral gate oxide layer 170, aperipheral gate electrode layer 180 and a first gate mask layer 190 aresequentially formed on the semiconductor structure where the trench maskpattern 110 was removed. The peripheral gate oxide layer 170 may be asilicon oxide layer formed using a thermal oxidation process and it maybe formed on top surfaces of the active regions of the low and highvoltage regions LVR and HVR. The peripheral gate oxide layer 170 isshown formed to a greater thickness in the high voltage region HVR thanthe low voltage region LVR and the cell array region CAR. The first gatemask layer 190 may be formed of a silicon oxide layer, for example, amedium temperature oxide (MTO).

Referring to FIGS. 10A and 10B, a second photoresist pattern is formedon the first gate mask layer 190, such that it covers the peripheralcircuit region. Subsequently, the first gate mask layer 190, theperipheral gate electrode layer 180 and the peripheral gate oxide layer170 are removed from the cell array region CAR using the secondphotoresist pattern as an etch mask, thereby exposing the top surface ofthe active region in the cell array region CAR.

The device isolation pattern 160 is etched to form a recessed deviceisolation pattern 165 exposing the top surface and upper sidewalls ofthe cell active region. The device isolation pattern 160 of theperipheral circuit region is not recessed and, as a result, it may havea top surface which is higher than or equal to the height of theperipheral active region. Forming the recessed device isolation pattern165 may include using an etch recipe having an etch selectivity withrespect to the semiconductor substrate 100. The etching processgenerally makes corners of a pattern rounded so that the top surface ofthe exposed cell active region may be further rounded as a result ofthis etching process.

The transistor formed in the cell array region CAR may have a fin-FETstructure by use of the recessed device isolation pattern 165, as seenin FIG. 13A. Here, a swing performance, a coupling ratio and a channelboosting performance of a fin-FET type transistor may be improvedcompared with those of a planar type transistor.

In some embodiments, removing the peripheral gate oxide layer 170 may beperformed using an etch solution containing hydrofluoric acid. Thus, thedevice isolation pattern 160 may be recessed while removing theperipheral gate oxide layer 170. Afterwards, the second photoresistpattern may be removed.

Referring to FIGS. 11A and 11B, a cell gate insulating layer, a cellgate electrode layer 230 and a second gate mask layer 240 aresequentially formed on the semiconductor device in a region includingthe recessed device isolation pattern 165. The cell gate insulatinglayer may include a tunnel insulating layer 200, a charge storage layer210 and a blocking dielectric layer 220.

The tunnel insulating layer 200 may be a silicon oxide layer formedusing a thermal oxidation process. The tunnel insulating layer 200 maybe locally formed on the exposed surface of the cell active region CARas shown in FIG. 11A (as compared to FIG. 11B). The thickness of thetunnel insulating layer 200 may range from about 10 Å to about 200 Å

The charge storage layer 210 may be an oxide and/or nitride of silicon,metal and/or metal silicide. For example, the charge storage layer 210may be a silicon nitride layer formed to a thickness ranging from about20 Å to about 200 Å

The blocking dielectric layer 220 may be formed of insulating materialshaving a higher dielectric constant than the charge storage layer 210.When the charge storage layer 210 is a silicon nitride layer, theblocking dielectric layer 220 may be one or more high dielectric layers,such as an aluminum oxide layer (Al₂O₃), a hafnium oxide layer (HfO₂) orthe like, and may have a thickness ranging from about 50 Å to about 300Å. When the blocking insulating layer 220 has a high dielectricconstant, a back-tunneling between a charge storage pattern (seereference numeral 215 of FIG. 13A) and a cell gate electrode (seereference numeral 235 of FIG. 13A), which will be formed in a followingprocess, may be decreased and the coupling ratio may be increased.Therefore, it is possible in some embodiments to form a floating traptype nonvolatile memory device more stably and effectively.

The cell gate electrode layer 230 may be formed of one or more metalnitrides. For instance, the cell gate electrode 230 may be a tantalumnitride (TaN) layer having a thickness ranging from about 100 Å to about1,000 Å. In addition, the second gate mask layer 240 may be formed ofthe same material, e.g., silicon oxide, as the first gate mask layer190.

Referring to FIGS. 12A and 12B, a third photoresist pattern is formedthat covers the cell array region CAR but exposes the peripheral circuitregion. Subsequently, the second gate mask layer 240, the cell gateelectrode layer 230, and the cell gate insulating layer are sequentiallyetched using the third photoresist pattern as an etch mask until thefirst gate mask layer 190 is exposed.

Thereafter, the third photoresist pattern is removed. Accordingly, thesecond gate mask layer 240 is exposed in the cell array region CAR, andthe first gate mask layer 190 is exposed in the peripheral circuitregion. The exposed first and second gate mask layers 190 and 240 areremoved to expose the cell gate electrode layer 230 and the peripheralgate electrode layer 180 in the cell array region CAR and the peripheralcircuit region, respectively. An upper gate electrode layer 250 isformed that covers the exposed cell gate electrode layer 230 and theexposed peripheral gate electrode layer 180. The upper gate electrodelayer 250 may be formed of one or more metal layers and/or metalsilicide layers.

Referring to FIGS. 13A and 13B, the upper gate electrode layer 250, thecell gate electrode layer 230 and the cell gate insulating layer arepatterned in the cell array region CAR to form cell gate patterns 260crossing over the cell active regions. The illustrated cell gate pattern260 includes a sequentially stacked tunnel insulating pattern 205, acharge storage pattern 215, a blocking dielectric pattern 225, a cellgate electrode 235 and an upper gate electrode 255.

As described above, due to the bird's beak occurring in forming thethermal oxide layer 130, the upper edges and top surface of the cellactive region are rounded. In some embodiments of the present invention,the existence of the preliminary cell trench 121 and/or the recess ofthe device isolation pattern 160 also affect the rounding of the celiactive region. The rounding of the cell active region causes theprotruded sidewall of the cell active region to have a more gentleslope. As a result, thickness dispersions of the upper gate electrodelayer 250 and the cell gate electrode 230 may be reduced. That is, inthe patterning process for forming the cell gate pattern 260, the uppergate electrode layer 250 and the cell gate electrode 230 can bepatterned while the problem of the conductive residue may be minimized.

In particular, according to some embodiments of the present invention,it is possible to minimize the recess depth of the device isolationpattern 160. For example, the recessed device isolation pattern 165 maybe recessed until the top surface of the recessed device isolationpattern 165 is equal in height to the edges of the top surface of thecell active region. In this case, as the cell active region has theconvex rounded surface, it is possible to limit or even prevent theformation of the conductive residue because of the round shape of thecell active region, which may provide performance advantages in theresulting fin-FET transistor.

Furthermore, the upper gate electrode layer 250 and the peripheral gateelectrode layer 180 are patterned in the peripheral circuit region toform the peripheral gate pattern 265 crossing over the peripheral activeregion. The peripheral gate pattern 265 includes the sequentiallystacked peripheral gate electrode 185 and the upper gate electrode 255.

FIG. 14 is a cross-sectional illustration of a semiconductor deviceaccording to some further embodiments of the present invention. Theillustrated embodiments of FIG. 14 are similar to the above-describedembodiments except that hemispherical silicon grains are formed in thecell active region. Thus, for the sake of conciseness, any repetitivedescription will be omitted herein.

Referring now to FIGS. 10A and 14, after forming the recessed deviceisolation pattern 165, a process of forming the hemispherical silicongrains is performed to form the hemispherical silicon grains on the topsurface and upper sidewalls of the exposed cell active region.Accordingly, effective surface areas of the cell active region and thecell gate insulating layer may be increased. As a result, thenonvolatile memory device may have an increased coupling ratio.

In some embodiments of the present invention, the top surface of thecell active region is rounded using the bird's beak phenomenon.Therefore, it is possible to reduce the conductive residue causing thegate bridge. In addition, as the transistor provided by some embodimentsof the present invention has the fin-FET structure, in which the deviceisolation pattern is recessed, the transistor may have enhanced swingperformance, coupling ratio and channel boosting performance incomparison with the conventional planar transistor.

As described above, some embodiments of the present invention providemethods of forming a semiconductor device capable of fabricating afin-FET with little or no conductive residue. Some embodiments provide amethod of forming a nonvolatile memory device that are suited for highintegration device fabrication. Semiconductor devices including afin-FET capable of restraining the occurrence of a conductive residueare also provided in some embodiments as well as a nonvolatile memorydevice that is suited for high integration devices.

The above-disclosed subject matter is to be considered illustrative, andnot restrictive, and the appended claims are intended to cover all suchmodifications, enhancements, and other embodiments, which fall withinthe true spirit and scope of the present invention. Thus, to the maximumextent allowed by law, the scope of the present invention is to bedetermined by the broadest permissible interpretation of the followingclaims and their equivalents, and shall not be restricted or limited bythe foregoing detailed description.

1. A semiconductor device comprising: a semiconductor substratecomprising a cell array region; cell device isolation patterns in thecell array region that define cell active regions having a convex uppersurface; and cell gate patterns crossing over the convex upper surfacesof the cell active regions and over the cell device isolation patterns.2. The semiconductor device of claim 1, wherein the convex uppersurfaces have a radius of curvature that is about 1/10 to about ½ of awidth thereof, and wherein a top surface of the cell device isolationpattern is lower than the convex upper surfaces.
 3. The semiconductordevice of claim 1, wherein the semiconductor substrate further comprisesa peripheral circuit region and wherein the device further comprises:peripheral device isolation patterns in the peripheral circuit regionthat define peripheral active regions; and a peripheral gate pattern onthe peripheral active regions, wherein the peripheral gate patternscomprise a stacked peripheral gate insulating layer and peripheral gateconductive layer and wherein the cell gate patterns comprise a stackedtunnel insulating layer, charge storage layer, blocking dielectric layerand cell gate electrode layer.
 4. The semiconductor device of claim 3,wherein the peripheral gate conductive layer comprises a polysiliconlayer, the cell gate electrode layer comprises a metal nitride, thecharge storage layer comprises an oxide and/or nitride of silicon, metaland/or metal silicide, and the blocking insulating layer comprises aninsulating material having a higher dielectric constant than adielectric constant of the charge storage layer.
 5. The semiconductordevice of claim 4, wherein the charge storage layer comprises a siliconnitride layer, the blocking dielectric layer comprises an aluminum oxidelayer, and the cell gate electrode layer comprises a tantalum nitridelayer.
 6. The semiconductor device of claim 3, wherein a height of a topsurface of the peripheral device isolation pattern is no less than aheight of a top surface of the peripheral active region.
 7. Thesemiconductor device of claim 3, wherein a first portion of theperipheral gate pattern comprises a low voltage transistor, and a secondportion of the peripheral gate pattern comprises a high voltagetransistor, wherein the peripheral gate insulating layer of theperipheral gate pattern comprising the high voltage transistor isthicker than the peripheral gate insulating layer of the peripheral gatepattern comprising the low voltage transistor.
 8. The semiconductordevice of claim 1, further comprising hemispherical silicon grainsbetween the cell active regions and the cell gate patterns, thehemispherical silicon grains extending from the semiconductor substrate.